The present invention relates generally to testing circuitry, and more specifically to testing circuitry for measuring the resistance of programmable elements in fuse link memory devices.
Generally, programmable memory devices have multiple memory cells which are connected by fuses to the bit lines of the memory device. The memory devices are programmed to provide a preferred bit arrangement by blowing appropriate fuses. A typical fuse is made from either polycrystalline silicon or nichrome strips, and therefore, provides a minimal resistance between the memory cell and corresponding bit line when the fuse is intact. A blown or programmed fuse, however, increases the resistance significantly between the respective memory cell and bit line, thereby substantially reducing the current flowing through the memory cell to the respective bit line upon the memory cell being activated.
Typically, a memory cell having an intact fuse provides a high level logic signal to the respective bit line upon being activated, while a memory cell having a programmed or blown fuse provides a low level logic signal to the bit line. Defective intact fuses, however, may have resistances outside a specified range and thus adversely affect the access times and programmability of those memory cells associated with the defective fuses. Additionally, a fuse which is believed to have been blown during the programming phase of the memory device may have only been marginally blown, resulting in the improper programming of the corresponding memory cell.
It is, therefore, an object of this invention to provide an improved memory device having a testing circuitry for testing the proper functioning of the memory cells and their corresponding fuses.
It is further an object of this invention to provide a testing circuitry for determining whether the fuses of a programmable memory device have resistances within a specified range in their pre-programmed state.
It is another object of this invention to provide a testing circuitry for determining whether the fuses which have been programmed in a programmable memory device have been properly blown.
These and other objects are attained by providing a testing circuit connected to the programmable fuses and having a means for varying the current flow through the same. A sensing amplifier having its input connected to a nodal point between the fuses and the testing circuit and its output connected to the output stage of the memory device is provided for sensing the current flow through the fuses during both the normal reading and testing operations of the memory device. During the testing operation, the current flow through the memory cell under test is varied by a known amount in response to specific logic input signals applied to the testing circuit. The sensing amplifier then provides a first output logic signal when the current flowing through the respective cell and fuse is below a specific threshold, and a second output logic signal when the current flowing through the respective cell and fuse is above a specific threshold. By varying the current flow through the fuse by specified amounts, the determination of the fuse resistance may be made from the output of the sensing amplifier, thereby revealing whether an intact fuse has the proper low resistance after manufacturing and whether a blown fuse has the proper high resistance after programming.
The means for varying the current in a preferred embodiment includes a variable resistance means having a series of resistors connected across a series of N-channel devices. The variable resistance means forms a voltage divider with the fuse such that the sensing amplifier input is connected at a nodal point therebetween. The testing circuit provides a first resistance during a normal read operation of the memory device and a second resisitance during a testing operation.
In another preferred embodiment, the means for varying current includes a variable current mirror formed of N-channel devices, whereby the output stage of the current mirror provides a current sink for the current flowing through the fuse. This preferred embodiment provides for a first current level during a normal read operation of the memory device and a second current level during a testing operation of the memory device.
The testing circuit may include a multiplexing switching means connected between the plurality of fuses and the sensing amplifier for multiplexing the programmable elements having these fuses with a single sensing amplifier. In the above preferred embodiments, the switching gate means includes an N-channel device having its source connected to the fuse of the programmable element and its drain connected to the input of the sensing amplifier. The gate of the switching gate means would thereby be triggered by multiplexing signals.
Although the preferred embodiments show the use of N-channel devices with an NPN matrix cell, the testing circuitry may also be used with other types of matrix cells. Additionally, either the variable resistance means or the means for varying current means may be implemented with P-channel devices or bipolar devices.
Other objects, advantages and novel features of the present invention will become apparent from the following detailed description of the invention when considered in conjunction with the accompanying drawings.